The present invention relates to the structure of a semiconductor device, especially to the structure of a plastic packaged semiconductor device and its fabrication method.
In recent years, in plastic packaged semiconductor devices, with an increased size of a pellet (chip), the dimension between the edge of a package and a semiconductor element tends to be increasingly smaller. This is because, although the semiconductor element has become large in size, the size of a package for housing it has been standardized and cannot be made larger. Accordingly, in order to solve such a problem, a plastic packaged semiconductor device of an LOC (Lead On Chip) structure as disclosed in Japanese Patent Kokoku Publication 6-105721 has come into use.
The plastic packaged semiconductor device of this LOC (Lead On Chip) structure is structured such that leads are bonded to the surface of a semiconductor element via insulating tapes, gold wire platings applied to the top surfaces of the leads and gold balls on the electrodes of the semiconductor element are connected by means of gold wires, and in addition, they are sealed by a resin material.
However, as a major problem with such conventional plastic packaged semiconductor devices, it sometimes happens, for example, that the function is impaired by a crack produced in the resin material due to the heat during the mounting on a board. If the resin becomes moist, having absorbed moisture while the semiconductor device is kept in the air, the moisture is vaporized due to the heat during the mounting on the board, and the force produced from it may bring about the crack. The insulating tape is particularly apt to absorb moisture, so that it often happens that a crack is produced from the area around the insulating tape. Further, as another problem, since there is the insulating tape, the reduction in the thickness of the semiconductor device is subject to a limitation.